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nj8820 absolute maximum ratings supply voltage, v dd 2 v ss input voltage open drain outputs, pins 3 and 13 all other pins storage temperature storage temperature 2 05v to 7v 7v v ss 2 03v to v dd 1 03v 2 65 c to 1 150 c (dg package, nj8820ma) 2 55 c to 1 125 c (dp and mp packages, nj8820) program enable (pe) osc in osc out d0 d1 d2 d3 f in v dd v ss latch 1 latch 2 latch 3 m counter (10 bits) control logic latch 4 latch 5 a counter (7 bits) frequency / phase detector v ss pda pdb lock detect (ld) modulus control output (mc) rb ch 15 16 17 f v reference counter (11bits) latch 6 latch 7 latch 8 4 2 sample / hold phase detector f r pulse detect sequence counter ds0 ds1 ds2 14 7 8 9 10 11 12 4 6 5 to internal latches memory enable (me) data select outputs 19 20 13 1 2 3 18 ? data inputs nj8820 frequency synthesiser (prom interface) fig.1 pin connections - top view t he nj8820 is a synthesiser circuit fabricated on the gps cmos process and is capable of achieving high sideband attenuation and low noise performance. it contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable m counter, 7-bit programmable a counter and the necessary control and latch circuitry for accepting and latching the input data. data is presented as eight 4-bit words read from an external memory, with the necessary timing signals generated internally. it is intended to be used in conjunction with a two-modulus prescaler such as the sp8710 series to produce a universal binary coded synthesiser. the nj8820 is available in plastic dil (dp) and miniature plastic dil (mp) packages, both with operating temperature range of 2 30 c to 1 70 c. the nj8820ma is available only in ceramic dil package with operating temperature range of 2 40 c to 1 85 c. ordering information nj8820 ba dp plastic dil package nj8820 ba mp miniature plastic dil package nj8820 ma dg ceramic dil package features n low power consumption n direct interface to rom or prom n high performance sample and hold phase detector n >10mhz input frequency fig.2 block diagram ch rb mc ds2 ds1 ds0 pe me d3 d2 pda pdb ld f in v ss v dd osc in osc out d0 d1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nj8820 ds3277-1.2 dp20, mp20, dg20
nj8820 f osc , f f in = 10mhz f osc , f f in = 10mhz i sink = 4ma i source = 1ma i sink = 2ma i source = 1ma i sink = 1ma i sink = 4ma i source = 5ma i sink = 5ma ttl compatible see note 1 v bias = self-bias point of pe (nominally v dd /2) ma ma v v v v v v v v v v m a v v v 55 15 04 7 04 04 04 7 04 6 01 075 supply current output levels memory enable output ( me) low level open drain pull-up voltage data select outputs (ds0-ds2) high level low level modulus control output ( mc) high level low level lock detect output ( ld) low level open drain pull-up voltage pdb output high level low level 3-state leakage current input levels data inputs (d0-d3) high level low level program enable input (pe) trigger level 46 46 46 425 v bias 6 100mv 2 electrical characteristics at v dd = 5v test conditions unless otherwise stated: v dd Cv ss =5v 05v. temperature range nj8820 ba: C30 c to +70 c; nj8820 ma: C40 c to +85 c dc characteristics value typ. max. characteristic min. 35 07 units conditions 0 to 5v square wave ? ac characteristics value typ. max. characteristic min. units conditions mvrms mhz ns m s m s ns ns k w nf k w v/rad m s 50 1 5 f in and osc in input level max. operating frequency, f f in and f osc propagation delay, clock to mc pe pulse length, t w data set-up time, t ds data hold time, t dh digital phase detector propagation delay gain programming resistor, rb hold capacitor, ch output resistance, pda digital phase detector gain power supply rise time 200 106 5 1 10 5 100 30 500 04 10mhz ac-coupled sinewave input squarewave v dd to v ss , see note 5. see note 2. pulse to v ss or v dd . see note 3. 10% to 90%, see note 4. notes 1. data inputs have internal pull-up resistors to enable them to be driven from ttl outputs. 2. all counters have outputs directly synchronous with their respective clock rising edges. 3. the finite output resistance of the internal voltage follower and on resistance of the sample switch driving this pin will add a finite time constant to the loop. an external 1nf hold capacitor will give a maximum time constant of 5 m s, typically. 4. to ensure correct operation of power-on programming. 5. operation at up to 15mhz is possible with a full logic swing but is not guaranteed.
nj8820 pin descriptions name description analog output from the sample and hold phase comparator for use as a fine error signal. output at (v dd 2 v ss )/2 when the system is in lock. voltage increases as f v phase lead increases; voltage decreases as f r phase lead increases. output is linear over only a narrow phase window, determined by gain (programmed by rb). three-state output from the phase/frequency detector for use as a coarse error signal. f v . f r or f v leading: positive pulses with respect to the bias point v bias f v , f r or f r leading: negative pulses with respect to the bias point v bias f v = f r and phase error within pda window: high impedance. an open-drain lock detect output at low level when phase error is within pda window (in lock); high impedance at all other times. the input to the main counters, normally driven from a prescaler, which may be ac-coupled or, when a full logic swing is available, may be dc-coupled. negative supply (ground). positive supply. these pins form an on-chip reference oscillator when a series resonant crystal is connected across them. capacitors of appropriate value are also required between each end of the crystal and ground to provide the necessary additional phase shift. an external reference signal may, alternatively, be applied to osc in. this may be a low-level signal, ac-coupled, or if a full logic swing is available it may be dc-coupled. the program range of the reference counter is 3 to 2047, with the division ratio being twice the programmed number. information on these inputs is transferred to the internal data latches during the appropriate data read time slot. d3 is msb, d0 is lsb. an open drain output for use in controlling the power supply to an external rom or prom. me is low during the data read period and high impedance at other times. a positive or negative pulse or edge ac-coupled into this pin initiates the single-shot data read procedure. grounding this pin repeats the data read procedure in a cyclic manner. internally generated three-state data select outputs, which may be used to address external memory. modulus control output for controlling an external dual-modulus prescaler. mc will be low at the beginning of a count cycle and will remain low until the a counter completes its cycle. mc then goes high and remains high until the m counter completes its cycle, at which point both a and m counters are reset. this gives a total division ratio of mp 1 a , where p and p 1 1 represent the dual-modulus prescaler values. the program range of the a counter is 0-127 and therefore can control prescalers with a division ratio up to and including 4 128/129. the programming range of the m counter is 8-1023 and, for correct operation, m > a . where every possible channel is required, the minimum total division ratio should be p 2 2 p . an external sample and hold phase comparator gain programming resistor should be connected between this pin and v ss . an external hold capacitor should be connected between this pin and v ss . pda pdb ld f in v ss v dd osc in/ osc out d0-d3 me pe ds0-ds2 mc rb ch 3 pin no. 1 2 3 4 5 6 7, 8 9,10, 11, 12 13 14 15, 16, 17 18 19 20 fig. 3 typical supply current v. input frequency fig. 4 typical supply current v. input level, osc in input level (v rms) 02 04 06 08 10 12 14 16 supply current (ma) 8 7 6 5 4 3 2 1 v dd = 5v f in = low frequency 0v to 5v square wave 10mhz 1mhz v dd = 5v osc in, f in = 0v to 5v square wave f in osc in input frequency (mhz) 1 2 3 4 5 6 7 8 9 10 supply current (ma) 20 15 10 05 total supply current is the sum of that due to f in and osc in
nj8820 programming program information can be obtained from an external rom or prom under the control of the nj8820. twenty-eight data bits are required per channel arranged as eight 4-bit words leaving four redundant bits, two of which are available on the data bus driving the data transfer time slot and may be used for external control purposes. a suitable prom would be the 74s287, giving up to 32 channel capability as shown in fig. 5. note that the choice of pnp transistor and supply bypass capacitor on the rom should be such that the rom will power up in time: for example, at 10mhz oscillator frequency, the rom must be powered up in less than 25 m s. reading this data is normally done in single shot mode, with the data read cycle started by either a positive or negative pulse on the program enable (pe) pin. the data read cycle is generated from a program clock at 1/64 of the reference oscillator frequency. a memory enable signal ( me) is supplied to allow power-down of the rom when it is not in use. data select outputs (ds0-ds2) remain in a high impedance state when the program cycle is completed to allow the address bus to be used for other functions if desired. the data map, data read cycle and timing diagram are shown in figs. 6 to 8. data is latched internally during the portions of the program cycle shown shaded in fig. 7 and all data is transferred to the counters and latched during the data transfer time slot. alternatively, the pe pin may be grounded, causing the data read cycle to repeat cyclically to allow continuous up-dating of the program information. in this mode, external memory will be enabled continuously ( me low) and the data read cycle will repeat every sixteen cycles of the internal program clock, i.e. every 1024/f osc seconds. this programming method is not recommended because the higher power consumption and the possibilities of noise into the loop from the digital data lines. power-on programming on power-up, the data read cycle is automatically initiated, making it unnecessary to provide a pe pulse. the circuit detects the power supply rising above a threshold point (nominally 15v) and, after an internally generated delay to allow the supply to rise fully, the circuit is programmed in the normal way. this delay is generated by counting reference oscillator pulses and is therefore dependent on the crystal used. the delay consists of 53248 reference oscillator cycles, giving a delay of about 5ms at 10mhz. to ensure correct operation of this function, the power supply rise time should be less than 5ms (at 10mhz), rising smoothly through the threshold point. fig. 5 programming via prom ds0 0 1 0 1 0 1 0 1 d3 m1 m5 m9 a3 - r3 r7 - d2 m0 m4 m8 a2 a6 r2 r6 r10 d1 - m3 m7 a1 a5 r1 r5 r9 d0 - m2 m6 a0 a4 r0 r4 r8 ds1 0 0 1 1 0 0 1 1 ds2 0 0 0 0 1 1 1 1 word 1 2 3 4 5 6 7 8 fig. 6 data map 4 ds2 ds1 ds0 pe me d3 d2 d0 d1 20 19 18 17 16 15 14 13 12 11 nj8820 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 11 10 9 74s287 1 2 3 4 5 6 7 8 a4-a7 (channel switch) 01 m 10 m 100k 1 5v 15k c1 47p c2b 22p c2a 22p c1 > c2a 1 c2b 1 ...
nj8820 4 program clock cycles from settling word 1 word 2 word 3 word 4 word 5 word 6 word 7 word 8 data transfer data transfer on 2 ve cycle of program clock program clock pe me ds0 ds1 ds2 fig.7 data selection phase comparators the digital phase/frequency detector drives a three-state output, pdb, which provides a coarse error signal to enable fast switching between channels. the pdb output is active until the phase error is within the sample and hold phase detector, pda, window, when pdb becomes high impedance. phase-lock is indicated at this point by a low level on ld. the sample and hold phase detector provides a fine error signal to give further phase adjustment and to hold the loop in lock. an internally generated ramp, controlled by the digital output from both the reference and main divider chains, is sampled at the reference frequency to give the fine error signal, pda. when in phase lock, this output would be typically at (v dd 2 v ss )/2 and any offset from this would be proportional to phase error. the relationship between this offset and the phase error is the phase comparator gain, which is programmable with an external resistor, rb. an internal 50pf capacitor is used in the sample and hold comparator. crystal oscillator when using the internal oscillator, the stability may be enhanced at high frequencies by the inclusion of a resistor between pin 8 (osc out) and the other components. a value of 22k w is advised. programming / power up data and signal input pins should not have input applied to them prior to the application of v dd , as otherwise latch-up may occur. 5 fig.8 timing diagram t w (pe internal) t ds t dh (data - internal mode) pe ds0 d0 - d3
nj8820 this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior knowledge the specification, design or price of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (0793) 518000 fax: (0793) 518411 gec plessey semiconductors p.o. box 660017 1500 green hills road, scotts valley, california 95067-0017, united states of america. tel: (408) 438 2900 fax: (408) 438 5576 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 fax : (1) 64 46 06 07 germany munich tel: (089) 3609 06-0 fax : (089) 3609 06-55 italy milan tel: (02) 66040867 fax: (02) 66040993 japan tokyo tel: (03) 5276-5501 fax: (03) 5276-5510 north america scotts valley, usa tel (408) 438 2900 fax: (408) 438 7023. south east asia singapore tel: (65) 3827708 fax: (65) 3828872 sweden stockholm, tel: 46 8 702 97 70 fax: 46 8 640 47 36 taiwan, roc taipei tel: 886 2 5461260. fax: 886 2 71900260 uk, eire, denmark, finland & norway swindon tel: (0793) 518510 fax : (0793) 518582 these are supported by agents and distributors in major countries world-wide. gec plessey semiconductors 1992
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